// Copyright (C) 2018  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// PROGRAM		"Quartus Prime"
// VERSION		"Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition"
// CREATED		"Wed Dec 09 00:00:20 2020"

module zl_2346_7(
	cp,
	rst_n,
	key_in,
	addr,
	DAC,
	freq,
	FTW
);


input wire	cp;
input wire	rst_n;
input wire	key_in;
output wire	[6:0] addr;
output wire	[7:0] DAC;
output wire	[23:0] freq;
output wire	[23:0] FTW;

wire	[6:0] SYNTHESIZED_WIRE_0;

assign	addr = SYNTHESIZED_WIRE_0;




zl_2346_7_1	b2v_inst(
	.cp(cp),
	.rst_n(rst_n),
	.key_in(key_in),
	.addr(SYNTHESIZED_WIRE_0),
	.freq(freq),
	.FTW(FTW));


ROM	b2v_inst1(
	.clock(cp),
	.address(SYNTHESIZED_WIRE_0),
	.q(DAC));


endmodule
